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Should we get another HCFX Pedal build going?


Bill Cosby

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I only see a total of an 8-pin opamp there

the ground and + is probably just his CAD program that powers both halves of the opamp. my guess.

besides, from what I'm seeing here, a special opamp isn't even needed. so yeah a common dual should work

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This is back on? Fantastic!

I don't want to hear new suggestions, clones, and there are enough fuzzes in the world (there, I said it). This has come so far already, and will be a real one off.

Well done guys, I wish I could help, but my pedal building skills have only recently hit BYOC. Godspeed gents.

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This is back on? Fantastic!


I don't want to hear new suggestions, clones, and there are enough fuzzes in the world (there, I said it). This has come so far already, and will be a real one off.


Well done guys, I wish I could help, but my pedal building skills have only recently hit BYOC. Godspeed gents.

 

 

This.

 

Also your avatar? Awesome, I think it's from a national geographic I have.

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This.


Also your avatar? Awesome, I think it's from a national geographic I have.

 

 

Hey thanks, I got obsessed with those little things when I was learning to scuba dive. I keep thinking about changing it though, a lot of people think it's a psychedelic mushroom.

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Someone PM me an address and I'll send the prototype we built to you. I'm sure the problem is related to having to float the +4.5V centerline for the op-amp, since the bleed is coming through the ground line. You can hear the timer even when the pedal is in bypass, and the only part of the pedal circuit still connected to the signal circuit in bypass is the ground.

 

My schematic drawing program is an old version of OrCAD. When I created the schematic symbol for the op-amp I told it that there were two parts in the package, and to show the power pins. The program ends up showing the power pins on both parts. So, yes - there is only one op-amp chip.

 

I suspect the problem is a combination of two things.

 

First, the fact that a phantom power rail had to be created at +4.5V in order to provide a centerline for the inherently bipolar op-amp. Any disproportionate current draw between R1 and R2 is going to make that +4.5V rail float around. It might be worth trying a 5V regulator instead of the R1/R2 voltage ladder. The rail doesn't have to be +4.5V - it just needs to keep the signal somewhere around the middle between 0V and +9V so that it isn't clipped by the op-amp.

 

Second, the output of the timer is going to be a square wave between a little more than 0V and a little less than +9V. The FET is only supposed to turn on for a very short time every cycle of the clock - just long enough to flash charge C4. The FET is then supposed to turn off, and C4 will hold the charge (or discharge very slowly into the input of the next op-amp) until the next clock pulse.

 

The first thing to do is to convert the square wave into a series of very short pulses, which is what C8 and R9 are doing. The rising edge of the square wave causes a brief positive pulse out of C8, while the falling edge causes a brief negative pulse. We don't want the negative pulse going to the gate of the FET, so it's blocked by CR1. R10 and R11 form a voltage ladder like R1 and R2, which set the baseline for the pulse that turns on the FET. Still, the pulses going to the gate of the FET should be controlled so that the gate isn't driven negative with respect to the +4.5V rail on the channel of the FET. If you can think of a better way to "shape" the clock signal going to the gate of the FET then you might reduce the clock noise quite a bit.

 

Anyway, I think the key is controlling the interaction between the artificial +4.5V power rail and the pulses from the clock circuit. The noise is difficult to see on my digital o-scope because the noise is travelling on the ground line, and my digital scope is ground referenced, meaning the noise is present on both the reference and the probe, so it cancels out.

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thanks for the additional info amp surgeon!
getting extremelly narrow pulses from the 555 isnt too hard, though personally I prefer using a 40106 or something.

so I guess some of us will take the existing schematic and tweak it in our own corners. it would be good to post the tweaks to see if advantages can be combined.

I havent looked at it yet. I only had 10 hours sleep between last friday, saturday and sunday so I pretty much just crashed last night. realistically, I'll probably only breadboard it next week, so dont count on me too much if you want something fast.

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thanks for the additional info amp surgeon!

getting extremelly narrow pulses from the 555 isnt too hard, though personally I prefer using a 40106 or something.

 

 

It's easy if you want a fixed frequency with a fixed duty cycle. It's pretty hard when you want a broad adjustable frequency range. The duty cycle changes with the frequency, and that's not what you want.

 

The objective is to get the FET to conduct just long enough for C4 to charge up to the instantaneous voltage coming out of U1A, but NOT long enough for the signal coming out of U1A to change by any significant amount. As long as the FET is conducting then the input on U1B is going to be whatever is coming out of U1A, and you don't want entire cycles or even portions of a cycle of the input signal getting through. You want "samples" of the input signal voltage at specific instants of time. This means the pulse on the gate has to be very short, regardless of the clock frequency.

 

The conventional way to do this is to use a couple of 555's - the first in astable mode, and the second in monostable mode. That seemed like overkill for this circuit, since a short time constant RC would do the trick. The pulses coming out of the RC circuit aren't square, but they don't need to be for this application.

 

Anyway, that's only half the problem, and probably not what's causing the clock noise. The 555 output goes close to 0V, which is way too low to be driving the gate on the FET. If the voltage on the gate goes even a little below +4.5V then the FET will glitch like crazy.

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